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SN65LVDS302
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SLLS733 - JUNE 2006
PROGRAMMABLE 27-BIT PARALLEL-TO-SERIAL RECEIVER
FEATURES
* * * Serial Interface Technology Compatible with FlatLinkTM3G such as SN65LVDS301 Supports Video Interfaces up to 24-bit RGB Data and 3 Control Bits Received over 1, 2 or 3 SubLVDS Differential Lines SubLVDS Differential Voltage Levels Up to 1.755 Gbps Data Throughput Three Operating Modes to Conserve Power - Active mode QVGA - 17mW - Typical Shutdown - 0.7 W - Typical Standby Mode - 27 W Typical Bus-Swap Function for PCB-Layout Flexibility ESD Rating > 4 kV (HBM) Pixel Clock Range of 4 MHz-65 MHz Failsafe on all CMOS Inputs Packaged in 5 mm x 5 mm MicroStar Junior BGA(R) with 0,5 mm Ball Pitch Very low EMI meets SAE J1752/3 'Kh'-spec The serial data and clock are received via Sub Low-Voltage Differential Signalling (SubLVDS) lines. The SN65LVDS302 supports three operating power modes (Shutdown, Standby and Active) to conserve power. When receiving, the PLL locks to the incoming clock CLK and generates an internal high-speed clock at the line rate of the data lines. The data is serially loaded into a shift register using the internal high-speed clock. The deserialized data is presented on the parallel output bus with a recreation of the Pixel clock PCLK generated from the internal high-speed clock. If no input CLK signal is present, the output bus is held static with the PCLK and DE held low, while all other parallel outputs are pulled high. The parallel (CMOS) output bus offers a bus-swap feature. The SWAP control pin controls the output pin order of the output pixel data to be either R[7:0]. G[7:0], B[7:0], VS, HS, DE or B[0:7]. G[0:7], R[0:7], VS, HS, DE. This gives a PCB designer the flexibility to better match the bus to the LCD driver pinout or to put the receiver device on the top side or the bottom side of the PCB. The F/S control input selects between a slow CMOS bus output rise time for best EMI and power consumption and a fast CMOS output for increased speed or higher load designs.
* * *
* * * * * * * * *
APPLICATIONS
Small Low-Emission Interface between Graphics Controller and LCD Display Mobile Phones & Smart Phones Portable Multimedia Players
DESCRIPTION
The SN65LVDS302 receiver de-serializes FlatLinkTM3G compliant serial input data to 27 parallel data outputs. The SN65LVDS302 receiver contains one shift register to load 30 bits from 1, 2 or 3 serial inputs and latches the 24 pixel bits and 3 control bits out to the parallel CMOS outputs after checking the parity bit. If the parity check confirms correct parity, the Channel Parity Error (CPE) output remains low. If a parity error is detected, the CPE output generates a high pulse while the data output bus disregards the new receive pixel. Instead, the last data word is held on the output bus for another clock cycle.
Flatlinka3G
LCD Driver LVDS302
CLK DATA
LVDS301
1 4 7
2 5 8 0
3 6 9 #
*
Application Processor with RGB Video Interface
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. FlatLink is a trademark of Texas Instruments. BGA is a registered trademark of Tessera, Inc.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2006, Texas Instruments Incorporated
SN65LVDS302
SLLS733 - JUNE 2006
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
Two Link Select lines LS0 and LS1 select whether 1, 2 or 3 serial links are used. The RXEN input may be used to put the SN65LVDS302 in a Shutdown mode. The SN65LVDS302 enters an active Standby mode if the common mode voltage of the CLK input becomes shifted to VDDLVDS (e.g., transmitter releases CLK output into high-impedance). This minimizes power consumption without the need of switching an external control pin. The SN65LVDS302 is characterized for operation over ambient air temperatures of -40C to 85C. All CMOS and SubLVDS signals are 2-V tolerant with VDD=0 V. This feature allows signal powerup before VCC is stabilized. FUNCTIONAL BLOCK DIAGRAM
RBBDC
VDDLVDS
D0+
50
iPCLK
SubLVDS
50
CPE SWAP F/S
1
Parity Check
AND
D0Serial-to-parallel conversion
RBBDC
VDDLVDS
8 8 8
R[0:7]
50
27-bit parallel Register
D1+
SubLVDS
50
0
0
G[0:7] B[0:7]
RBBDC
VDDLVDS
1
D2+
50 50
Output Buffer
D1-
HS VS
SubLVDS
D2VDDLVDS
RGB=1 HS=VS=1 DE=0
standby or pwr down
x10, x15, or x30
DE
RBBDC
CLK+
50
SubLVDS
50
PLL multiplier
x1
CLK-
iPCLK
0
PCLK
1
standby
Vthstby
CPOL
RXEN LS0 LS1
Glitch Suppression
Control
2
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SN65LVDS302
SLLS733 - JUNE 2006
PINOUT - TOP VIEW
PINOUT - TOP VIEW
1
2
3
4
5
6
7
8
9
A
GND R 6/B 1 R 4/B 3 R 2/B 5 R 0/B 7 G 6/G 1 G 4/G 3 G 2/G 5 GND
B
R 7/B 0 R 5/B 2 R 3/B 4 R 1/B 6 G 7/G 0 G 5/G 2 G 3/G 4 G 1/G 6 G 0/G 7
C
LS 0 VDD VDD GND VDD GND B 7/R 0 B 6/R 1
D
D 2+ LS 1 GND GND GND GND VDD B 5 /R 2 B 4 /R 3
E
D 2GND PLLD GND GND GND GND VDD B 3/R 4 B 2/R 5
F
D 1+ V DDPLLD GND GND GND GND VDD B 1/R 6 B 0/R 7
G
D 1GND LVDS GND GND GND GND VDD F /S PCLK
H
CPOL V DDLVDS V DDPLLA GND PLLA V DDLVDS GND LVDS GND VS HS
J
GND LVDS SWAP CLK + CLK D 0+ D 0RXEN DE CPE
RGB Output pin assignment based on SWAP pin setting: SWAP = 0 / SWAP =1
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SN65LVDS302
SLLS733 - JUNE 2006
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PINOUT - TOP VIEW (continued) SWAP PIN FUNCTIONALITY
The SWAP pin allows the pcb designer to reverse the RGB bus, thus minimize potential signal crossovers due to signal routing. The two drawings beneath show the RGB signal pin assignment based on the SWAP-pin setting.
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
A R6 B R7 C B7 D B5 E B4 B6 R5 R3 R1 G7 G5 G3 G1 G0 R4 R2 R0 G6 G4 G2
A B1 B B0 C R0 D R2 E B3 B2 F B1 B0 G PCLK PCLK H VS HS J DE DE VS HS R3 R1 B2 B4 B6 G0 G2 G4 G6 G7 B3 B5 B7 G1 G3 G5
F
SN65LVDS302 Top View
SN65LVDS302 Top View
R4
R5
R6
R7
G
H
J
Figure 1. Pinout With SWAP PIN = GND
Figure 2. Pinout With SWAP PIN = VDD
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SN65LVDS302
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PINOUT - TOP VIEW (continued)
Table 1. Pin Description
PIN A1 A2 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B8 B9 SWAP - L H L H L H L H L H L H L H - L H L H L H L H L H L H L H L H L H SIGNAL GND R6 B1 R4 B3 R2 B5 R0 B7 G6 G1 G4 G3 G2 G5 GND R7 B0 R5 B2 R3 B4 R1 B6 G7 G0 G5 G2 G3 G4 G1 G6 G0 G7 PIN C1 C2 C3 C4 C5 C6 C7 C8 C9 D1 D2 D3 D4 D5 D6 D7 D8 D9 E1 E2 E3 E4 E5 E6 E7 E8 E9 - - - - L H L H - - - - - - - L H L H - - - - - - - L H L H SWAP . - - SIGNAL LS0 VDD unpopulated VDD GND VDD GND B7 R0 B6 R1 D2+ LS1 GND GND GND GND VDD B5 R2 B4 R3 D2- GNDPLLD GND GND GND GND VDD B3 R4 B2 R5 PIN F1 F2 F3 F4 F5 F6 F7 F8 F9 G1 G2 G3 G4 G5 G6 G7 G8 G9 H1 H2 H3 H4 H5 H6 H7 H8 H9 J1 J2 J3 J4 J5 J6 J7 J8 J9 SWAP - - - - - - - L H L H - - - - - - - - - - - - - - - - - - - - - - - - - - - SIGNAL D1+ VDDPLLD GND GND GND GND VDD B1 R6 B0 R7 D1- GNDLVDS GND GND GND GND VDD F/S PCLK CPOL VDDLVDS VDDPLLA GNDPLLA VDDLVDS GNDLVDS GND VS HS GNDLVDS SWAP CLK+ CLK- D0+ D0- RXEN DE CPE
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SN65LVDS302
SLLS733 - JUNE 2006
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TERMINAL FUNCTIONS
NAME D0+, D0- D1+, D1- SubLVDS in D2+, D2- CLK+, CLK- R0-R7 G0-G7 B0-B7 HS VS DE PCLK LS0, LS1 CMOS OUT I/O DESCRIPTION SubLVDS Data Link (active during normal operation) SubLVDS Data Link (active during normal operation when LS0 = high and LS1 = low, or LS0 = low and LS1=high; high impedance if LS0 = LS1 = low); input can be left open if unused SubLVDS Data Link (active during normal operation when LS0 = low and LS1 = high, high-impedance when LS1 = low); input can be left open if unused SubLVDS Input Pixel Clock; Polarity is fixed. Red Pixel Data (8); pin assignment depends on SWAP pin setting Green Pixel Data (8); pin assignment depends on SWAP pin setting Blue Pixel Data (8); pin assignment depends on SWAP pin setting Horizontal Sync Vertical Sync Data Enable Output Pixel Clock; rising or falling clock polarity is selected by control input CPOL Link Select (Determines active SubLVDS Data Links and PLL Range) See Table 2 Disables the CMOS Drivers and Turns Off the PLL, putting device in shutdown mode 1 - Reciver enabled 0 - Receiver disabled (Shutdown) RXEN Note: RXEN input incorporates glitch suppression logic to avoid unwanted switching. The input must be pulled low for longer than 10s continuously to force the receiver to enter Shutdown. The input must be pulled high for at least 10s continuously to activate the receiver. An input pulse shorter than 5us will be interpreted as glitch and becomes ignored. At power up, the receiver is enabled immediately if RXEN=H and disabled if RXEN=L CMOS In CPOL Output Clock Polarity Selection 0 - rising edge clocking 1 - falling edge clocking Bus Swap swaps the bus pins to allow device placement on top or bottom of pcb. See pinout drawing for pin assignments. 0 - data output from R7...B0 1 - data output from B0...R7 CMOS bus rise time select F/S 1 - fast output rise time 0 - slow output rise time Channel Parity Error This output indicates the detection of a parity error by generating an output high-pulse for half of a PCLK clock cycle; This allows counting parity errors with a simple counter. 0 - no error high-pulse - bit error detected VDD GND VDDLVDS GNDLVDS VDDPLLA GNDPLLA VDDPLLD GNDPLLD Power Supply Supply Voltage Supply Ground SubLVDS I/O supply Voltage SubLVDS Ground PLL analog supply Voltage PLL analog GND PLL digital supply Voltage PLL digital GND
SWAP
CPE
CMOS Out
6
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SN65LVDS302
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FUNCTIONAL DESCRIPTION Deserialization Modes
The SN65LVDS302 receiver has three modes of operation controlled by link-select pins LS0 and LS1. Table 2 shows the deserializer modes of operation. Table 2. Logic Table: Link Select Operating Modes
LS1 0 0 1 1 LS0 0 1 0 1 1ChM 2ChM 3ChM Mode of Operation 1-channel mode (30-bit serialization rate) 2-channel mode (15-bit serialization rate) 3-channel mode (10-bit serialization rate) Reserved Data Links Status D0 active; D1, D2 disabled D0, D1 active; D2 disabled D0, D1, D2 active Reserved
1-Channel Mode While LS0, LS1 are held low the SN65LVDS302 will receive payload data over a single SubLVDS data pair, D0. The PLL will lock to the SubLVDS clock input and internally multiply the clock by a factor of 30. The internal high speed clock will be used to shift in the data payload on D0 and deserialize 30 bits of data. Figure 3 illustrates the timing and the mapping of the data payload into the 30-bit frame. The internal high speed clock is divided back down by a factor of 30 to recreate the pixel clock and the data payload with pixel clock is presented on the output bus. The reserved bits and parity bit are not output. While in this mode the PLL can lock to a clock that is in the range of 4MHz through 15MHz. This mode is intended for smaller video display formats that do not need to utilize the full bandwidth capabilities of the SN65LVDS302.
CLK CLK + D0 +/- CHANNEL res res CP R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 VS HS DE res res CP R7 R6
Figure 3. Data and Clock Input in 1-ChM (LS0 and LS1 = low) 2-Channel Mode While LS0 is held high and LS1 is held low the SN65LVDS302 will receive payload data over two SubLVDS data pairs, D0 and D1. The PLL will lock to the SubLVDS clock input and internally multiply the clock by a factor of 15. The internal high speed clock will be used to shift in the data payload on D0 and D1, and will deserialize 15 bits of data from each pair. Figure 4 illustrates the timing and the mapping of the data payload into the 30-bit frame. The internal high speed clock is divided back down by a factor of 10 to recreate the pixel clock and the data payload with pixel clock is presented on the output bus. The reserved bits and parity bit are not output. While in this mode the PLL can lock to a clock that is in the range of 8 MHz through 30 MHz.
CLK CLK + D0 +/- CHANNEL CP R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 VS res CP R7 R6 D1 +/- CHANNEL res G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 HS DE res G3 G2
Figure 4. Data and Clock Output in 3-ChM (LS0 = high; LS1 = low)
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SN65LVDS302
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3-Channel Mode While LS0 is held low and LS1 is held high the SN65LVDS302 will receive payload data over three SubLVDS data pairs: D0, D1 and D2. The PLL will lock to the SubLVDS clock input and internally multiply the clock by a factor of 10. The internal high speed clock will be used to shift in the data payload on D0, D1 and D2 and will deserialize 10 bits of data from each pair. Figure 5 illustrates the timing and the mapping of the data payload into the 30-bit frame. While in this mode the PLL can lock to a clock that is in the range of 20MHz through 65 MHz.
CLK CLK + D0 +/- CHANNEL CP R7 R6 R5 R4 R3 R2 R1 R0 VS CP R7 R6 D1 +/- CHANNEL res G7 G6 G5 G4 G3 G2 G1 G0 HS res G7 G6 D2 +/- CHANNEL res B7 B6 B5 B4 B3 B2 B1 B0 DE res B7 B6
Figure 5. Data and Clock Output in 3-ChM (LS0 = low; LS1 = high)
POWERDOWN MODES
The SN65LVDS302 Receiver has two powerdown modes to facilitate efficient power management.
SHUTDOWN MODE
A low input signal on RXEN pin puts the SN65LVDS302 into Shutdown mode. This turns off most of the receiver circuitry including the SubLVDS receivers, PLL, and deserializers. The subLVDS differential-input resistance remains 100- while any input signal becomes ignored. All outputs will hold a static output pattern: R[0:7]=G[0:7]=B[0:7]=VS=HS=high; DE=PCLK=low. The current draw in Shutdown mode will be nearly zero if the subLVDS inputs are left open or pulled high.
STANDBY MODE
The SN65LVDS302 will enter the Standby mode when the SN65LVDS302 is not in Shutdown mode but the SubLVDS clock-input common-mode voltage is above 0.9 x VDDLVDS. The CLK input incorporates a pull-up circuit to shift the SubLVDS clock-input common-mode voltage to VDDLVDS in the absence of an input signal. All circuitry except the SubLVDS clock-input Standby monitor is shut down. The SN65LVDS302 will also enter Standby mode when the input clock frequency on the CLK input is less than 500 kHz. The SubLVDS input resistance remains 100 while any input signal on the data inputs D0, D1, and D2 becomes ignored. All outputs will hold a static output pattern: R[0:7]=G[0:7]=B[0:7]=VS=HS=high; DE=PCLK=low. The current drawn in Standby mode will be very low.
ACTIVE MODES
A high input signal on RXEN combined with a CLK input signal switching faster than 3 MHz and VICM smaller than 1.3 V force the SN65LVDS302 into Active mode. Current consumption in active mode depends on operating frequency and the number of data transitions in the data payload. CLK-input frequencies between 3 MHz and 4 MHz activate the device but proper PLL functionality is not secured. It is not recommended to operate the SN65LVDS302 in active mode at CLK frequencies below 4MHz.
ACQUIRE MODE (PLL Approaches Lock)
When the SN65LVDS302 is enabled and a SubLVDS clock input present, the PLL will pursue lock to the input clock. While the PLL pursues lock the output data bus will hold a static output pattern: R[0:7]=G[0:7]=B[0:7]=VS=HS=high; DE=PCLK=low.
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SN65LVDS302
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For proper device operation, the pixel clock frequency must fall within the valid fPCLK range specified under recommended operating conditions. If the pixel clock frequency is larger than 3 MHz but smaller than fPCLK(min), the SN65LVDS302 PLL is enabled. Under such conditions, it is possible for the PLL to lock temporarily to the pixel clock, causing the PLL monitor to release the device into active receive mode. If this happens, the PLL may or may not be properly locked to the pixel clock input, potentially causing data errors, frequency oscillation, and PLL deadlock (loss of VCO oscillation).
RECEIVE MODE
After the PLL achieves lock the device enters the normal receive mode. The output data bus presents the de-serialized data. The PCLK output pin outputs the recovered pixel clock. PARITY ERROR DETECTION AND HANDLING The SN65LVDS302 receiver performs error checking on the basis of a parity bit that is transmitted across the subLVDS interface from the transmitting device. Once the SN65LVDS302 detects the presence of the clock and the PLL has locked onto PCLK, then the parity is checked. Parity-error detection ensures detection of all single bit errors in one pixel and 50% of all multi-bit errors. The parity bit covers the 27 bit data payload consisting of 24 bits of pixel data plus VS, HS and DE. Odd Parity bit signalling is used. The parity error is output on the output CPE pin. If the sum of the 27 data bits and the parity bit result in an odd number, the receive data are assumed to be valid. The CPE output will be held low. If the sum equals an even number, parity error is declared. The CPE output will indicate high for half a PCLK period. The CPE output will be set with the data bit transition and cleared after 1/2 the data bit time. This allows counting every detected parity error with a simple counter connected to CPE.
A Parity error is signalized by a high-pulse on CPE; the width of the pulse is 1/2 the length of a PCLK cycle
CPE
R[0:7], G[0:7], B[0:7], HS, VS, DE
Also if there is a parity error detected then the data on that PCLK cycle is not output.Instead, the last valid data from a previous PCLK cycle is repeated on the output bus. This is to prevent any bit error that may occur on the LVDS link from causing perturbations in VS, HS or DE that may be visually disruptive to a display. The reserved bits are not covered in the parity calculations.
When a parity error was detected, the receiver outputs the previous pixel on the bus. Hence no data transitions occur.
PCLK (CPOL=0)
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SN65LVDS302
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STATUS DETECT AND OPERATING MODES FLOW DIAGRAM
The SN65LVDS302 switches between the power saving and active modes in the following way:
Power Up RXEN Low Power Up RXEN = 1
ShutDown
RXEN High
Standby
VICM(CLK) > 0.9 VDDLVDS RXEN Low VICM(CLK) > 0.9 VDDLVDS or fCLK < 500 kHz CLK Input Power Up RXEN = 1
Receive RXEN Low
PLL Achieved Lock
Acquire
Table 3. Status Detect and Operating Modes Descriptions
Mode Shutdown Mode Characteristics Least amount of power consumption (most circuitry turned off); All outputs held static: R[0:7]=G[0:7]=B[0:7]=VS=HS=high DE=PCLK=low; Low power consumption (Standby monitor circuit active; PLL is shutdown to conserve power); All outputs held static: R[0:7]=G[0:7]=B[0:7]=VS=HS=high DE=PCLK=low; PLL pursues lock; All outputs held static: R[0:7]=G[0:7]=B[0:7]=VS=HS=high DE=PCLK=low; Data transfer (normal operation); receiver deserializes data and provides data on parallel output Conditions RXEN is set low for longer than 10s
(1) (2)
Standby Mode
RXEN is high for longer than 10us and both CLK input common mode VICM(CLK) above 0.9xVDDLVDS or CLK input floating (2) RXEN is high; CLK input monitor detected clock input common mode and woke up receiver out of Standby mode RXEN is high and PLL is locked to incoming clock
Acquire Mode
Transmit Mode
(1) (2)
In Shutdown Mode, all SN65LVDS302 internal switching circuits (e.g., PLL, serializer, etc.) are turned off to minimize power consumption. The input stage of any input pin remains active. Leaving CMOS control inputs unconnected can cause random noise to toggle the input stage and potentially harm the device. All CMOS inputs must be tied to a valid logic level VIL or VIH during Shutdown or Standby Mode. An exception are the subLVDS inputs CLK and Dx, which can be left unconnected while not in use.
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SN65LVDS302
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Table 4. Operating Mode Transitions
MODE TRANSITION USE CASE 1. RXEN high > 10 s 2. Receiver enters standby mode a. R[0:7]=G[0:7]=B[0:7]=VS=HS remain high and DE=PCLK low b. Receiver activates clock input monitor Standby Acquire Receiver activity detected 1. CLK input monitor detects clock input activity; 2. Outputs remain static; 3. PLL circuit is enabled Acquire Receive Link is ready to receive data 1. PLL is active and approaches lock 2. PLL achieves lock within twakeup 3. D1, D2, and/or D3 become active depending on LS0 and LS1 selection 4. first Data word was recovered 5. Parallel output bus turns on switching from static output pattern to output first valid data word Receive Standby Transmitter requested to enter Standby mode by input common mode voltage VICM > 0.9 VDDLVDS (e.g. transmitter output clock stops or enters high-impedance state) Turn off Receiver 1. Receiver disables outputs within tsleep 2. RX Input monitor detects VICM > 0.9 VDDLVDS within tsleep 3. R[0:7]=G[0:7]=B[0:7]=VS=HS transition to high and DE=PCLK to low on next falling PLL clock edge 4. PLL shuts down. Clock activity input monitor remains active. 1. RXEN pulled low for > tpwrdn 2. Receiver switches all outputs into high-impedance state 3. Most IC circuitry is shut down for least power consumption TRANSITION SPECIFICS Shutdown Standby Drive TXEN high to enable receiver
Receive/Standby Shutdown
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SN65LVDS302
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ABSOLUTE MAXIMUM RATINGS (1)
VALUE Supply voltage range, VDD
(2),
UNIT V V kV V
VDDPLLA, VDDPLLD, VDDLVDS
-0.3 to 2.175 -0.5 to 2.175 -0.5 to VDD + 2.175 4 1500 200 5
Voltage range at any input When VDDx > 0 V or output terminal When VDDx 0 V Human Body Model (3) (all Pins) Electrostatic discharge Charged-Device Mode (4) (all Pins) Machine Model (5) (all pins) Continuous power dissipation Ouput current, IO (1) (2) (3) (4) (5)
See Dissipation Rating Table mA
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the GND terminals. In accordance with JEDEC Standard 22, Test Method A114-B. In accordance with JEDEC Standard 22, Test Method C101. In accordance with JEDEC Standard 22, Test Method A115-A
DISSIPATION RATINGS
PACKAGE ZQE (1) (2) CIRCUIT BOARD MODEL Low-K (2) TA < 25C 592 mW DERATING FACTOR (1) ABOVE TA = 25C 7.407 mW/C TA = 85C POWER RATING 148 mW
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. In accordance with the Low-K thermal metric definitions of EIA/JESD51-2.
DEVICE POWER DISSIPATION
PARAMETER TEST CONDITIONS VDDx = 1.8 V, TA = 25C, all outputs terminated with 10 pF VDDx = 1.95 V, TA = -40C, all outputs terminated with 10 pF fCLK at 4 MHz fCLK at 65 MHz fCLK at 4 MHz fCLK at 65 MHz TYP 16.8 64.7 27.4 128.8 MAX UNIT mW mW
PD
Device Power Dissipation
12
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SN65LVDS302
SLLS733 - JUNE 2006 (1)
RECOMMENDED OPERATING CONDITIONS
VDD VDDPLLA VDDPLLD VDDLVDS
MIN Supply voltages Test set-up see Figure 7 VDDn(PP) Supply voltage noise magnitude 50MHz (all supplies) fCLK 50MHz; f(noise) = 1Hz to 2 GHz fCLK > 50MHz; f(noise) = 1Hz to 1MHz fCLK > 50 MHz; f(noise) > 1MHz TA Operating free-air temperature 1-Channel transmit mode, see Figure 3 fCLK Input Pixel clock frequency 2-Channel transmit mode, see Figure 4 3-Channel transmit mode, see Figure 5 Standby mode (2), See Figure 16 tDUTCLK |VID| VICM VICM CLK Input Duty Cycle Magnitude of differential input voltage Input Voltage Common Mode Range Input Voltage Common Mode Variation between all SubLVDS inputs Differential Input Voltage Amplitude Variation between all SubLVDS inputs Input Rise and Fall Time Input Rise or Fall Time mismatch between all SubLVDS inputs High-level input voltage Low-level input voltage RXEN input pulse duration Output load capacitance |VD0+-VD0-|, |VD1+-VD1-|, |VD2+-VD2-|, |VCLK+-VCLK-| during normal operation Receive or Acquire mode Stand-by mode VICM(n)- VICM(m) with n=D0, D1, D2, or CLK and m=D0, D1, D2, or CLK VID(n)- VID(m) with n=D0, D1, D2, or CLK and m=D0, D1, D2, or CLK RXEN at VDD; see figure 6-2 tR(n)- tR(m) and tF(n)- tF(m) with n=D0, D1, D2, or CLK and m=D0, D1, D2, or CLK -100 35 70 0.6 0.9 x VDDLVDS -100 D0+, D0-, D1+, D1-, D2+, D2-, CLK+, and CLK- -40 4 8 20 CLK+ and CLK- 1.65
TYP 1.8
MAX 1.95
UNIT V
100 100 40 85 15 30 65 500 65 200 1.2 100
mV
C
MHz kHz %
mV V
mV -10 10 % 800 100 ps ps
VID
tR/F tR/F
LS0, LS1, CPOL, SWAP, RXEN, F/S VICMOSH VICMOSL tinRXEN CL (1) (2) 0.7xVDD 0 10 10 VDD 0.3xVDD V V s pF
R[7:0], G[7:0], B[7:0], VS, HS, PCLK, CPE
Unused single-ended inputs must be held high or low to prevent them from floating. PCLK input frequencies lower than 500 kHz force the SN65LVDS302 into standby mode. Input frequencies between 500 kHz and 3 MHz may or may not activate the SN65LVDS302. Input frequencies beyond 3 MHz activate the SN65LVDS302. Input frequencies between 500kHz and 4MHz are not recommended, and can cause PLL malfunction.
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SN65LVDS302
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DEVICE ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS Alternating 1010 Test pattern (see Table 9); All CMOS outputs terminated with 10pF; F/S and RXEN at VDD; VIH=VDD, VIL=0 V; VDD=VDDPLLA=VDDPLLD=VDDLVDS; 1ChM Typical power test pattern (see Table 6); VID=70 mV, All CMOS outputs terminated with 10pF; F/S at GND and RXEN at VDD; VIH=VDD, VIL=0 V; VDD=VDDPLLA=VDDPLLD=VDDLVDS; Alternating 1010 Test pattern (seeTable 9); All CMOS outputs terminated with 10pF; F/S and RXEN at VDD; VIH=VDD, VIL=0 V; VDD=VDDPLLA=VDDPLLD=VDDLVDS; 2ChM IDD RMS Supply Current Typical power test pattern (see Table 7); VID=70 mV, All CMOS outputs terminated with 10pF; F/S at GND and RXEN at VDD; VIH=VDD, VIL=0 V; VDD=VDDPLLA=VDDPLLD=VDDLVDS; Alternating 1010 Test pattern (see Table 9); All CMOS outputs terminated with 10pF; F/S and RXEN at VDD; VIH=VDD, VIL=0 V; VDD =VDDPLLA=VDDPLLD=VDDLVDS; 3ChM Typical power test pattern (see Table 8); VID=70 mV, All CMOS outputs terminated with 10pF; F/S at GND and RXEN at VDD; VIH=VDD, VIL=0 V; VDD =VDDPLLA=VDDPLLD=VDDLVDS; fPCLK = 4 MHz fPCLK = 6 MHz fPCLK = 15 MHz fPCLK = 4 MHz fPCLK = 6 MHz fPCLK = 15 MHz fPCLK = 8 MHz fPCLK = 22 MHz fPCLK = 30 MHz fPCLK = 8 MHz fPCLK = 22 MHz fPCLK = 30 MHz fPCLK = 20 MHz fPCLK = 65 MHz fPCLK = 20 MHz fPCLK = 65 MHz Standby mode; RXEN=VIH Shutdown mode; RXEN=VIL MIN TYP (1) 9.8 11.7 19.3 4.7 6.0 13.2 14.3 25.0 26.8 6.4 13.7 18.3 17.1 60.8 8.6 22.2 15 100 mA 27.0 68.0 mA mA 19.4 33.0 37.0 mA mA MAX 14.0 15.9 25.0 mA UNIT
CLK and D[0:2] inputs are left open; All control inputs held static high or low; All CMOS outputs terminated with 10pF; VIH=VDD, VIL=0V; VDD=VDDPLLA=VDDPLLD=VDDLVDS
A A
0.4
10
(1)
All typical values are at 25C and with 1.8 V supply unless otherwise noted.
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INPUT ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER D0+, D0-, D1+, D1-, D2+, D2-, CLK+, and CLK- Vthstby Input voltage common mode threshold to RXEN at VDD switch between receive/acquire mode and standby mode Low-level differential input voltage threshold High-level differential input voltage threshold Input leakage current Power-off input current Differential input termination resistor value Input capacitance Input capacitance variation Measured between input terminal and GND Within one signal pair Between all signals 21 II= -18mA, VDD=VDD(min) 0VVDD1.95V; VI=GND or VI=1.95V 2 VIN = 0.7 x VDD VIN = 0.3 x VDD -200 -200 0.7xVDD 0 200 200 VDD 0.3xVDD 30 VDD=1.95 V; VI+ = VI-; VI = 0.4 V and VI = 1.5 V VDD=GND; VI = 1.5V 78 100 1 0.2 1 39 -1.2 100 VD0+-VD0-, VD1+-VD1-, VD2+-VD2-, VCLK+-VCLK1.3 0.9xVDDLVDS V -40 40 75 -75 122 mV mV A A pF pF k V nA pF nA V TEST CONDITIONS MIN TYP (1) MAX UNIT
VTHL VTHH II+, II- IIOFF RID CIN CIN
RBBDC Pull-up resistor for standby detection LS0, LS1, CPOL, SWAP, RXEN, F/S VIK Input clamp voltage IICMOS Input current (2) CIN IIH IIL VIH VIL (1) (2) Input capacitance High-level input current Low-level input current High-level input voltage Low-level input voltage
All typical values are at 25C and with 1.8 V supply unless otherwise noted. Do not leave any CMOS Input unconnected or floating to minimize leakage currents. Every input must be connected to a valid logic level VIH or VOL while power is supplied to VDD.
OUTPUT ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER R[0:7], G[0:7], B[0:7], VS, HS, PCLK, CPE 1-ChM, F/S=L, IOH=-250 A VOH High-level output current 2-or 3-ChM, F/S=L, IOH=-500 A 1-ChM, F/S=H, IOH=-500 A 2- or 3-ChM, F/S=H, IOH=-2.0 mA 1-ChM, F/S=L, IOL=250 A VOL Low-level output current 2- or 3-ChM, F/S=L, IOL=500 A 1-ChM, F/S=H, IOL=500 A 2- or 3-ChM, F/S=H, IOL=2.0 mA IOH High-level output current 1-ChM, F/S=L 2- or 3-ChM, F/S=L; 1-ChM, F/S=H 2- or 3-ChM, F/S=H IOL Low-level output current 1-ChM, F/S=L 2- or 3-ChM, F/S=L; 1-ChM, F/S=H 2- or 3-ChM, F/S=H -250 -500 -2000 250 500 2000 A 0 0.2xVDD V 0.8xVDD VDD V TEST CONDITIONS MIN TYP MAX UNIT
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SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER D0+, D0-, D1+, D1-, D2+, D2-, CLK+, and CLK- tR/F tR/F Input rise and fall time Input rise or fall time mismatch between all SubLVDS inputs RXEN at VDD; see figure 6-2 tR(n)- tR(m) and tF(n)- tF(m) with n=D0, D1, D2, or CLK and m=D0, D1, D2, or CLK -100 800 100 ps ps TEST CONDITIONS MIN TYP (1) MAX UNIT
R[7:0], G[7:0], B[7:0], VS, HS, PCLK, CPE 1-channel mode, F/S=L 2-channel mode, F/S=L tR/F Rise and fall time 20%- 80% of VDD (2) CL = 10 pF (3); see Figure 9 3-channel mode, F/S=L 1-channel mode, F/S=H 2-channel mode, F/S=H 3-channel mode, F/S=H 1-channel and 3-channel mode tOUTP PCLK output duty cycle CPOL=VIL, 2-channel mode CPOL=VIH, 2-channel mode tOSK Output skew between PCLK and R[0:7], G[0:7], B0:7], HS, VS, and DE see Figure 9 -500 500 ps 8 4 4 4 1 1 45% 48% 41% 50% 53% 47% 16 8 8 8 2 2 55% 59% 52% ns
INPUT TO OUTPUT RESPONSE TIME tPD(L) tGS tpwrup tpwrdn Propagation delay time from CLK+ input to PCLK output RXEN Glitch suppression pulse width (4) Enable time from power down (RXEN) Disable time from active mode (RXEN) RXEN at VDD, VIH=VDD, VIL=GND, CL=10 pF, See Figure 14 VIH=VDD, VIL=GND, RXEN toggles between VIL and VIH; See Figure 15 and Figure 16 Time from RXEN pulled high to data outputs enabled and transmit valid data; See Figure 16 RXEN is pulled low during receive mode; time measurement until all outputs held static: R[0:7]=G[0:7]=B[0:7]=VS=HS=high, DE=PCLK=low and PLL is Shutdown; See Figure 16 RXEN at VDD; device is in standby; time measurement from CLK input starts switching to PCLK and data outputs enabled and transmit valid data; See Figure 17 RXEN at VDD; device is receiving data; time measurement from CLK input signal stops (input open or input common mode VICM exceeds threshold voltage Vthstby) until all outputs held static: R[0:7]=G[0:7]=B[0:7]=VS=HS=high, DE=PCLK=low and PLL is Shutdown; See Figure 17 Tested from CLK input to PCLK output 2-ChM; fPCLK=22MHz 3-ChM; fPCLK=65MHz 0.087xfPCLK 0.075xfPCLK 1.4/fPCLK 1.9/fPCLK 2.5/fPCLK 3.8 2 s s ms
11
s
twakeup
Enable time from Standby (CLK)
2
ms
tsleep
Disable time from active mode (CLK transitions to high-impedance)
3
s
fBW
PLL bandwidth (5)
MHz
(1) (2) (3) (4) (5)
All typical values are at 25C and with 1.8 V supply unless otherwise noted. tR/F depends on the F/S setting and the capacitive load connected to each output. Some application information of how to calculate tR/F based on the output load and how to estimate the timing budget to interconnect to an LCD driver are provided in the application section near the end of this data sheet. The output rise and fall time is optimized for an output load of 10 pF. The rise and fall time can be adjusted by changing the output load capacitance. The RXEN input incorporates a glitch-suppression logic to disregard short input pulses. tGS is the duration of either a high-to-low or low-to-high transition that is suppressed. When using the SN65LVDS302 receiver in conjunction with the SN65LVDS301 transmitter in one link, the PLL bandwidth of the SN65LVDS302 receiver always exceed the bandwidth of the SN65LVDS301 transmit PLL. This ensures stable PLL tracking under all operating conditions and maximized the receiver skew margin.
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9.0
12 11
4 MHz 9%
8.5
8 MHz 9%
20 MHz 8.7 %
PLL BW (% of PCLK Frequency)
10
Spec Limit 1 ChM
Spec Limit 2 ChM 30 MHz 8.1 %
PLL - Bandwidth - %
8.0
Spec Limit 3 ChM
9 8 7 6
15 MHz 8.1 %
7.5
65 MHz 7.5 %
7.0
6.5
5 4 0
6.0
100
200
300 400 500 PLL - Frequency - MHz
600
700
0
10
20
50 30 40 PCLK - Frequency - MHz
60
70
Figure 6. SN65LVDS302 PLL Bandwidth (also showing the SN65LVDS301 PLL bandwidth)
TIMING CHARACTERISTICS
PARAMETER TEST CONDITIONS 1ChM: x=0..29, fPCLK=15 MHz; RXEN at VDD, VIH=VDD, VIL=GND, RL=100 , test setup as in Figure 8, test pattern as in Table 11 2ChM: x = 0..14, fPCLK =30 MHz RXEN at VDD, VIH=VDD, VIL=GND, RL=100 , test setup as in Figure 8, test pattern as in Table 12 3ChM: RXEN at VDD, VIH=VDD, VIL=GND, test setup as in Figure 8, test pattern as in Table 13 fCLK=15 MHz (4) fCLK=4 MHz to 15 MHz (5) MIN 630
1 - 480 ps 2 * 30 * fCLK
MAX
UNIT
fCLK=30 MHz (4) fCLK=8 MHz to 30 MHz (5)
630
tRSKMx
(1) (2)
Receiver input skew margin; see (3) and Figure 43
1 - 480 ps 2 * 15 * fCLK
fCLK= 65 MHz (4) fCLK = 20 MHz to 65 MHz (5) 360
ps
1 - 410 ps 2 * 10 * fCLK
(1) (2) (3)
(4) (5)
Receiver Input Skew Margin (tRSKM) is the timing margin available for transmitter output pulse position (tPPOS), interconnect skew, and interconnect inter-symbol interference. tRSKM represents the reminder of the serial bit time not taken up by the receiver strobe uncertainty;. The tRSKM assumes a bit error rate better than 10-12. tRSKM is indirect proportional to the internal set-up and hold time uncertainty, ISI and duty cycle distortion from the front end receiver, the skew missmatch between CLK and data D0, D1, and D2, as well as the PLL cycle-to-cycle jitter. This includes the receiver internal set-up and hold time uncertainty, all PLL related high-frequent random and deterministic jitter components that impact the jitter budget, ISI and duty cycle distortion from the front end receiver, and the skew between CLK and data D0, D1, and D2; The pulse position min/max variation is given with a bit error rate target of 10-12; Measurements of the total jitter are taken over a sample amount of > 10-12 samples. The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temp ranges. These Minimum and Maximum Limits are simulated only.
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PARAMETER MEASUREMENT INFORMATION
SN65LVDS302
1 2
VDDPLLA 10 F
VDDPLLD VDD VDDLVDS GND
Noise Generator 100 mV
1W
Note: The generator regulates the noise amplitude at point 1 to the target amplitude given under the table recommended operating conditions the test
1.6 H
1.8 V Supply
Figure 7. Power Supply Noise Test Set-Up
To measure t RSKM, CLK is advanced or delayed with respect to data until errors are observed at the receiver outputs. The advance or delay is then reduced until there are no data errors observed over 10-12 serial bit times. The magnitude of the advance or delay is tRSKM Programmable delay CLK and Data Pattern Generator CLK D1 D2 D3 DUT: SN65LVDS302 Bit error Detector
tPG_ERROR
Ideal receiver strobe position
TRSKM(p)
C tbit
TRSKM(n)
tRSKM tPG_ERROR tbit C
- is the smaller of the two measured values tRSKM(p) and tRSKM(n) - Test equipment (pattern generator) intrinsic output pulse position timing uncertainty - serial bit time - LVDS302 set-up and hold-time uncertainty
Note: C can be derived by subtracting the receiver skew margin t RSKM(p) + tRSKM(p) from one serial bit time
Figure 8. Jitter Budget
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PARAMETER MEASUREMENT INFORMATION (continued)
tF t setup
R[7:0], G[7 :0 ], B[7:0], HS, VS ,
80% (VOH -V OL )
DE
20% (VOH -V OL )
t OSK
t hold
tR VOH
80% (VOH -V OL )
PCLK
(CPOL=0)
50% (VOH OL) -V
20% (VOH -VOL ) VOL
tF
tR
Note: The Set-up and Hold-time of CMOS outputs R[7:0], G[7:0], B[7:0], HS, VS, and DE in relation to PCLK can be calulated by: 1 tS&H = 2 -r -t -t - DtDUTP PCLK REF OSK
Figure 9. Output Rise/Fall, Setup/Hold Time
VDx+ -VDx- , VCLK+ -VCLK 80%(VID) tf
100%(VIC)
tr
0V
20%(VID) 0%(VID)
Figure 10. SubLVDS Differential Input Rise and Fall Time Defintion
CLK+, Dx+
VDDLVDS R BBDC
RID /2
Gain Stage
RID/2 CLK-, DxStandby detection line end termination
ESD
Figure 11. Equivalent Input Circuit Design
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PARAMETER MEASUREMENT INFORMATION (continued)
I ICMOS
SWAP, CPOL, LSx, RXEN, F/S
CMOS Input (V I++V I-)/2 V ICMOS V ID I I+ CLK+, Dx+ I ICLK-, DxV ICM V I+ V ISubLVDS Input CMOS Output VO RGB, VS, HS, CPE PCLK IO
Figure 12. I/O Voltage and Current Definition
RGB, VS, HS, CPE, PCLK VO
SN65LVDS302 CL=10 pF
Figure 13. CMOS Output Test Circuit, Signal and Timing Definition
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PARAMETER MEASUREMENT INFORMATION (continued)
R7(n-1)
R7(n-2)
pixel (n-1) R7 (n)
R7 R6 R5 R4 CP R7
pixel ( n)
pixel (n+1 ) R7(n+1) CP R7
D0 + CLK CLK +
t PD(L)
VDD/2
PCLK (CPOL=0)
CMOS data out
pixel (n-1)
R7
R7(n-3)
R7(n-1)
R6
R6(n-3)
R6(n-1)
Figure 14. Propagation Delay Input to Output (LS0=LS1=0)
V DD /2 RXEN t GS
CLK
t PLL VCO internal signal PLL approaches lock t pwrup PCLK
R[7:0],G[7:0],B[7:0], DE, VS, HS
Figure 15. Receiver Phase Lock Loop Set TIme and Receiver Enable Time
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PARAMETER MEASUREMENT INFORMATION (continued)
3 ms Glitch shorter than t GS will be ignored <20 ns 2 ms
less than 20ns Spike will be rejected
Glitch shorter than tGS will be ignored
RXEN tpwrup PCLK tpwrdn
I CC CLK
tGS tGS
Receiver disabled (OFF)
Receiver aquires lock
Receiver enabled (ON)
RX RXdisabled turns (OFF ) OFF
Figure 16. Receiver Enable/Disable Glitch Suppression Time
CLK t wakeup t sleep
PCLK
R[7:0], G[7:0], B[7:0], VS, HS,
Receiver disabled (OFF)
Receiver aquires lock, outputs still disabled
RX enabled output data valid
RX enabled; output data invalid
RX disabled (OFF)
Figure 17. Standby Detection
POWER CONSUMPTION TESTS
Table 5 shows an example test pattern word. Table 5. Example Test Pattern Word
Word 1 7 0 1 1 1 1 1 C 0 0 0 0 R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE 0x7C3E1E7 3 1 1 1 1 E B6 0 1 0 0 1 B5 0 B4 1 B3 1 B2 1 E B1 1 B0 0 0 0 1 7 VS HS DE 1 1
R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7
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TYPICAL IC POWER CONSUMPTION TEST PATTERN
The typical power consumption test patterns consists of sixteen 30-bit transmit words in 1-channel mode, eight 30-bit transmit words in 2-channel mode and five 30-bit transmit words in 3-channel mode. The pattern repeats itself throughout the entire measurement. It is assumed that every possible transmit code on RGB inputs has the same probability to occur during typical device operation. Table 6. Typical IC Power Consumption Test Pattern, 1-Channel Mode
Word 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Test Pattern: R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE 0x0000007 0xFFF0007 0x01FFF47 0xF0E07F7 0x7C3E1E7 0xE707C37 0xE1CE6C7 0xF1B9237 0x91BB347 0xD4CCC67 0xAD53377 0xACB2207 0xAAB2697 0x5556957 0xAAAAAB3 0xAAAAAA5
Table 7. Typical IC Power Consumption Test Pattern, 2-Channel Mode
Word 1 2 3 4 5 6 7 8 Test Pattern: R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE 0x0000001 0x03F03F1 0xBFFBFF1 0x1D71D71 0x4C74C71 0xC45C451 0xA3aA3A5 0x5555553
Table 8. Typical IC Power Consumption Test Pattern, 3-Channel Mode
Word 1 2 3 4 5 Test Pattern: R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE 0xFFFFFF1 0x0000001 0xF0F0F01 0xCCCCCC1 0xAAAAAA7
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MAXIMUM POWER CONSUMPTION TEST PATTERN
The maximum (or worst-case) power consumption of the SN65LVDS302 is tested using the two different test pattern shown in table. test patterns consists of sixteen 30-bit transmit words in 1-channel mode, eight 30-bit transmit words in 2-channel mode and five 30-bit transmit words in 3-channel mode. The pattern repeats itself throughout the entire measurement. It is assumed that every possible transmit code on RGB inputs has the same probability to occur during typical device operation. Table 9. Worst-Case Power Consumption Test Pattern
Word 1 2 Test Pattern: R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE 0xAAAAAA5 0x5555555
Table 10. Worst-Case Power Consumption Test Pattern
Word 1 2 Test Pattern: R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE 0x0000000 0xFFFFFF7
OUTPUT SKEW PULSE POSITION and JITTER PERFORMANCE
The following test patterns are used to measure the output skew pulse position and the jitter performance of the SN65LVDS302. The jitter test pattern stresses the interconnect particularly to test for ISI, very long run-lengths of consecutive bits, incorporates very high and low data rates, and maximizes switching noise. Each pattern is self-repeating for the duration of the test. Table 11. Transmit Jitter Test Pattern, 1-Channel Mode
Word 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Test Pattern: R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE 0x0000001 0x0000031 0x00000F1 0x00003F1 0x0000FF1 0x0003FF1 0x000FFF1 0x0F0F0F1 0x0C30C31 0x0842111 0x1C71C71 0x18C6311 0x1111111 0x3333331 0x2452413 0x22A2A25 0x5555553 0xDB6DB65 0xCCCCCC1 0xEEEEEE1 0xE739CE1 0xE38E381
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Table 11. Transmit Jitter Test Pattern, 1-Channel Mode (continued)
Word 23 24 25 26 27 28 29 30 31 32 Test Pattern: R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE 0xF7BDEE1 0xF3CF3C1 0xF0F0F01 0xFFF0001 0xFFFC001 0xFFFF001 0xFFFFC01 0xFFFFF01 0xFFFFFC1 0xFFFFFF1
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Table 12. Transmit Jitter Test Pattern, 2-Channel Mode
Word 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Test Pattern: R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE 0x0000001 0x000FFF3 0x8008001 0x0030037 0xE00E001 0x00FF001 0x007E001 0x003C001 0x0018001 0x1C7E381 0x3333331 0x555AAA5 0x6DBDB61 0x7777771 0x555AAA3 0xAAAAAA5 0x5555553 0xAAA5555 0x8888881 0x9242491 0xAAA5571 0xCCCCCC1 0xE3E1C71 0xFFE7FF1 0xFFC3FF1 0xFF81FF1 0xFE00FF1 0x1FF1FF1 0xFFCFFC3 0x7FF7FF1 0xFFF0007 0xFFFFFF1
Table 13. Transmit Jitter Test Pattern, 3-Channel Mode
Word 1 2 3 4 5 6 7 8 9 10 11 26 Test Pattern: R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE 0x0000001 0x0000001 0x0000003 0x0101013 0x0303033 0x0707073 0x1818183 0xE7E7E71 0x3535351 0x0202021 0x5454543 Submit Documentation Feedback
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Table 13. Transmit Jitter Test Pattern, 3-Channel Mode (continued)
Word 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Test Pattern: R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE 0xA5A5A51 0xADADAD1 0x5555551 0xA6A2AA3 0xA6A2AA5 0x5555553 0x5555555 0xAAAAAA1 0x5252521 0x5A5A5A1 0xABABAB1 0xFDFCFD1 0xCAAACA1 0x1818181 0xE7E7E71 0xF8F8F81 0xFCFCFC1 0xFEFEFE1 0xFFFFFF1 0xFFFFFF5 0xFFFFFF5
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TYPICAL CHARACTERISTIC CURVES
Some of the plots in this section show more than one curve representing various device pin relationships. Taken together, they represent a working range for the tested parameter.
SUPPLY CURRENT vs TEMPERATURE
30 25
2-Channel Mode, 11 MHz (HVGA), F/S = 1 2-Channel Mode, 22 MHz (VGA), F/S = 1
QUIESCENT SUPPLY CURRENT vs TEMPERATURE
100.0
STANDBY 10.0
2-Channel Mode, 22 MHz (VGA), F/S = 0
20
IDD - mA
15 10 5 0 -50 -30 -10 10 30 Temperature - C 50 70 90
2-Channel Mode, 11 MHz (HVGA), F/S = 0
IDDQ - mA
1.0
POWERDOWN 0.1 -50
-30
-10
10 30 50 Temperature - C
70
90
Figure 18. SUPPLY CURRENT vs FREQUENCY, 1-CHANNEL MODE
40 35 30
1-ChM F/S=0, jitter test
Figure 19. SUPPLY CURRENT vs FREQUENCY, 2-CHANNEL MODE
40 35 30 25
IDD - mA
2-ChM, F/S=1 jitter test
25
IDD - mA
20 15 10 5 0
1ChM, F/S=1, jitter test
20 15 10
2-ChM, F/S=0 jitter test
2-ChM typ pwr
1-ChM, typ pwr
5 0
0
2
4
6
8
10
12
14
16
18
20
0
5
10
15
20
25
30
Frequency - MHz
Frequency - MHz
Figure 20. SUPPLY CURRENT vs FREQUENCY, 3-CHANNEL MODE
40 35 30
3-ChM, F/S=1 jitter test
Figure 21. RECEIVER STROBE POSITION vs TEMPERATURE
450 400 350 300
FL3G Limit 3-ChM 56MHz (XGA) 2-ChM 22MHz (VVGA) Limit with RSKM=130ps
t(RSPOS)
25
IDD - mA
250 200 150
20 15 10 5 0
3-ChM, F/S=0 jitter test
3-ChM 65MHz 1-ChM 11MHz (HVGA)
3-ChM typ pwr
100 50 15 20 25 30 35 40 45 50 55 60 0 -40 -20
0
Frequency - MHz
20 40 Temperature - C
60
80
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TYPICAL CHARACTERISTIC CURVES (continued)
PLL Bandwidth
12.0
3-ChM 3-ChM 3-ChM 2-ChM
PCLK Cycle-to-Cycle output jitter
900 800
10.0 8.0 6.0 4.0 2.0
Spec Limit 2ChM 8MHz: 9% 2-ChM
Spec Limits 3-Ch Mode
3-ChM Spec Limit 3ChM
700 600
1-ChM
PLL Bandwidth - %
CC Jitter - ps
Spec Limits 1-Ch Mode
Spec Limits 2-Ch Mode
500 400 300 200
3-ChM
100 0.0 0.0 0 10.0 20.0 30.0 40.0 50.0 Frequency - MHz 60.0 70.0 0 10
2-ChM
20
30 40 50 Frequency - MHz
60
70
Figure 24. RSKM, 1-CHANNEL MODE vs BIT RATE
2000
Figure 25.
Receiver Strobe Position uncertainty
1500
T(PPOS )
1000
Additional interconnect margin
500
RSKM - ps
225
0
-225 -
Minimum desired Interconnect Budget
-500
-1000
-1500
-2000
120
170
220
270 dR - Mbps
320
370
420
Bit width
Trskm 1ChM
Trskm - Tppos
225ps
Figure 26.
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TYPICAL CHARACTERISTIC CURVES (continued)
RSKM, 2-CHANNEL MODE vs BIT RATE
2000 1500
Trskm Bit width
RSKM, 3-CHANNEL MODE vs BIT RATE
2000 1500
Bit width
1000 500
Trskm - Tppos
1000 500
Trskm - Tppos 225ps
Trskm
Time - ps
Time - ps
225ps
0 -500 -1000 -1500 -2000 120
225ps Trskm - Tppos Trskm Bit width
0 -500 -1000 -1500 -2000 200
225ps Trskm - Tppos Trskm Bit width
170
220
270 320 dR - Mbps
370
420
250
300
350
400 450 dR - Mbps
500
550
600
650
Figure 27. QVGA OUTPUT WAVEFORM
249 250
Figure 28. VGA 2-CHANNEL OUTPUT WAVEFORM
190
190
Output Voltage Amplitude - mV
0
1-Channel Mode, f(PCLK) = 5.5 MHz
Output Voltage Amplitude - mV
0
2-Channel Mode, f(PCLK) = 22 MHz
-190 -251 1 ns/div Response Over 80-inch of FR-4 + 1m Coax Cable
-190 -250 500 ps/div Response Over 8-inch FR-4 + 1m Coax Cable
Figure 29. VGA 2-CHANNEL OUTPUT WAVEFORM
249 249
Figure 30. VGA3-CHANNEL OUTPUT WAVEFORM
190
190
Output Voltage Amplitude - mV
Output Voltage Amplitude - mV
0
2-Channel Mode, f(PCLK) = 22 MHz
0
3-Channel Mode, f(PCLK) = 22 MHz
-190 -251 500 ps/div Response Over 80-inch FR-4 + 1m Coax Cable
-190 -251 1 ns/div Response Over 80-inch FR-4 + 1m Coax Cable
Figure 31.
Figure 32.
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TYPICAL CHARACTERISTIC CURVES (continued)
XGA 3-CHANNEL OUTPUT WAVEFORM
249
XGA 3-CHANNEL OUTPUT WAVEFORM
190
Output Voltage Amplitude - mV
0
Output Voltage Amplitude - mV 400 mV/div
3-Channel Mode, f(PCLK) = 56 MHz
-190 -251
3-Channel Mode, f(PCLK) = 56 MHz 300 ps/div Response Over 80-inch FR-4 + 1m Coax Cable 3.5 ns/div Response With 1-pF Load
Figure 33. INPUT COMMON-MODE NOISE REJECTION vs FREQUENCY
0.0 -2.0 -4.0
Differential S11 - dB
Figure 34.
INPUT RETURN LOSS
0.0
-10.0
-6.0
CMNR - dB
-20.0
-8.0 -10.0 -12.0 -14.0 -16.0
-30.0
-40.0
-50.0 -18.0 -20.0 0 -60.0 200 400 600 800 1000 1200 1400 1600 1800 2000 Frequency - kHz 0 200 400 600 800 1000 1200 1400 1600 1800 2000 Frequency - kHz
Figure 35. INPUT DIFFERENTIAL CROSSTALK vs FREQUENCY
0.0 -10.0
Differential Xtalk - dB
-50 -60 -70 -80 -90
Figure 36. PHASE NOISE
-20.0 -30.0
dBc/Hz
-100 -110 -120 -130 -140
f(PCLK) = 65 MHz
-40.0 -50.0 -60.0 -70.0 -80.0 0 200 400 600 800 1000 1200 1400 1600 1800 2000 Frequency - kHz
-150 -160 -170 -180
1
10
100
1k
10k
100k
1M
10M
FREQUENCY - Hz
Figure 37.
Figure 38.
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TYPICAL CHARACTERISTIC CURVES (continued)
GTEM SAE J1752/3 EMI test
30
f(PCLK)=62 MHz
25
RADIATED EMISSION - dBmV
20
15
10
5
0
0
200
400
600
800
1000
FREQUENCY - MHz
1200
1400
1600
1800
2000
Figure 39.
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SN65LVDS302
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APPLICATION INFORMATION Preventing Increased Leakage Currents in Control Inputs
A floating (left open) CMOS input allows leakage currents to flow from VDD to GND. Do not leave any CMOS Input unconnected or floating. Every input must be connected to a valid logic level VIH or VOL while power is supplied to VDD. This also minimizes the power consumption of standby and power down mode.
Power Supply Design Recommendation
For a multilayer pcb, it is recommended to keep one common GND layer underneath the device and connect all ground terminals directly to this plane.
SN65LVDS302 DECOUPLING RECOMMENDATION
The SN65LVDS302 was designed to operate reliably in a constricted environment with other digital switching ICs. In cell phone designs, the SN65LVDS302 often shares a power supply with various other ICs. The SN65LVDS302 can operate with power supply noise as specified in Recommend Device Operating Conditions. To minimize the power supply noise floor, provide good decoupling near the SN65LVDS302 power pins. The use of four ceramic capacitors (two 0.01 F and two 0.1 F) provides good performance. At the very least, it is recommended to install one 0.1 F and one 0.01 F capacitor near the SN65LVDS302. To avoid large current loops and trace inductance, the trace length between decoupling capacitor and IC power inputs pins must be minimized. Placing the capacitor underneath the SN65LVDS302 on the bottom of the PCB is often a good choice.
VGA APPLICATION
Figure 40 shows a possible implementation of a standard 640x480 VGA display. The LVDS301 interfaces to the SN65LVDS302, which is the corresponding receiver device to deserialize the data and drive the display driver. The pixel clock rate of 22MHz assumes ~10% blanking overhead and 60Hz display refresh rate. The application assumes 24-bit color resolution. It is also shown, how the application processor provides a powerdown (reset) signal for both serializer and the display driver. The signal count over the Flexible Printed Circuit board (FPC) could be further decreased by using the standby option on the SN65LVDS302 and pulling RXEN high with a 30k resistor to VDD.
2x0.1uF
GND 2.7V
FPC
GND 2.7 V
2x0.1uF
2x0.01uF
2x0.01uF
GND
VDDx
Application Processor (e.g. OMAP)
VDDx
GND
1.8V GND
1. 8V GND
Video Mode Display Driver
CLK+ CLK-
22MHz
Pixel CLK D[7:0] D[15:8] D[23:16] HS,VS,DE
22MHz
PCLK R[7:0] G[7:0] B[7:0] HS,VS,DE SN65LVDS 301
D0+ D0D1+ D1-
330Mbps
CLK+ CLKD0+ D0D1+ D1-
PCLK R[7:0] G[7:0] B[7:0] HS,VS,DE
22MHz
330Mbps
27
27
RESET
TXEN
RXEN
LS1
LS1
ENABLE
SN65LVDS 302
SPI
LS0
LS0
1. V 8
1.8V If FPC wire count is critical replace this , connection with a pull up resistor at RXEN 3
Serial port interface (3-wire ) IF
Figure 40. Typical VGA Display Application
SPI
LCD with VGA resolution
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APPLICATION INFORMATION (continued) DUAL LCD-DISPLAY APPLICATION
The example in Figure 41 shows a possible application setup driving two video mode displays from one application processor. The data rate of 330Mbps at a pixel clock rate of 5.5MHz corresponds to 320x240 QVGA resolution at 60Hz refresh rate and 10% blanking overhead.
2x0.1uF 2x0.01 uF GND 2. 7V FPC GND 2. 7V 2x0.1uF 2x0.01 uF
GND
VDDx
Pixel CLK D[ 5: 0] D[ 11 : 6] D[ 17 : 12 ] HS, VS, DE
5.5MHz
PCLK R[ 5: 0] G[ 5: 0] B[ 5: 0] HS, VS, DE SN 65LVDS 301
CLK+ CLKD0+ D0-
CLK+ 5.5MHz CLKD0+ 330 Mbps D0-
PCLK R[ 5: G[ 5: B[ 5: HS, VS, 0] 0] 0] DE
PCLK EN SIN SOUT SCLK
18 +3
SN65LVDS 302
Display Driver
TXEN
SCLK SI N SOUT SEL2 SEL1
LS1
LS1
RXEN
LS0
LS0
PCLK 1.8V 1.8V EN SIN SOUT SCLK
Figure 41. Example Dual-QVGA Display Application
TYPICAL APPLICATION FREQUENCIES
The SN65LVDS302 supports pixel clock frequencies from 4 MHz to 65 MHz over 1, 2, or 3 data lanes. Table 14 provides a few typical display resolution examples and shows the number of data lanes necessary to connect the SN65LVDS302 with the display. The blanking overhead is assumed to be 20%. Often, blanking overhead is smaller, resulting in a lower data rate. Furthermore, the examples in the table assumes a display frame refresh rate of 60-Hz. The actual refresh rate may differ depending on the application-processor clock implementation. Table 14. Typical Application Data Rates and Serial Lane Usage
Display Screen Resolution 176x220 (QCIF+) 240x320 (QVGA) 640x200 352x416 (CIF+) 352x440 320x480 (HVGA) 800x250 640x320 640x480 (VGA) 1024x320 854x480 (WVGA) 800x600 (SVGA) 1024x768 (XGA) Visible Pixel Count 38,720 76,800 128,000 146,432 154,880 153,600 200,000 204,800 307,200 327,680 409,920 480,000 786,432 Blanking Overhead 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% Display Refresh Rate 90 Hz 60 Hz 60 Hz 60 Hz 60 Hz 60 Hz 60 Hz 60 Hz 60 Hz 60 Hz 60 Hz 60 Hz 60 Hz Pixel Clock Frequency [MHz] 4.2 MHz 5.5 MHz 9.2 MHz 10.5 MHz 11.2 MHz 11.1 MHz 14.4 MHz 14.7 MHz 22.1 MHz 23.6 MHz 29.5 MHz 34.6 MHz 56.6 MHz Serial Data Rate Per Lane 1-ChM 125 Mbps 166 Mbps 276 Mbps 316 Mbps 335 Mbps 332 Mbps 432 Mbps 442 Mbps 138 Mbps 158 Mbps 167 Mbps 166 Mbps 216 Mbps 221 Mbps 332 Mbps 354 Mbps 443 Mbps 221 Mbps 236 Mbps 295 Mbps 346 Mbps 566 Mbps 2-ChM 3-ChM
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LCD wit h QVGA resolut ion
LCD with QVGA resolution
2
Application Processor (e.g. OMAP )
GND
GND
VDDx
GND
1. 8V
1. 8V
Display Driver 21
1
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CALCULATION EXAMPLE: HVGA DISPLAY
The following calculation shows an example for a Half-VGA display with the following parameters: Display Resolution: Frame Refresh Rate: Vertical Visible Pixel: Vertical Front Porch: Vertical Sync: Vertical Back Porch: Horizontal Visible Pixel: Horizontal Front Porch: Horizontal Sync: Horizontal Back Porch: 320 x 480 58.4 Hz 480 lines 20 lines 5 lines 3 lines 320 columns 10 columns 5 columns 3 columns
VFP=10 Visible area =320 lines Vsync =5 VBP =3 Hsync =5
HBP
Visible area = 480 column
HFP=20
Visible area
Entire Display
Figure 42. HVGA Display
Calculation of the total number of pixel and Blanking overhead: Visible Area Pixel Count: 480 x 320 = 153600 pixel Total Frame Pixel Count: (480+20+5+3) x (320+10+5+3) = 173304 pixel Blanking Overhead: (173304-153600) / 153600 = 12.8 %
The application requires following serial-link parameters: Pixel Clk Frequency: Serial Data Rate: 173304 x 58.4 Hz = 10.1 MHz 1-channel mode: 10.4 MHz x 30 bit/channel = 304 Mbps 2-channel mode: 10.4 MHz x 15 bit/channel = 152 Mbps
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How To Determine Interconnect Skew and Jitter Budget
Designing a reliable data link requires examining the interconnect skew and jitter budget. The sum of all transmitter, pcb, connector, FPC, and receiver uncertainties must be smaller than the available serial bit time. The highest pixel clock frequency defines the available serial bit time. The transmitter timing uncertainty is defined by tPPOS in the transmitter data sheet. For a bit-error-rate target of 10-12, the measurement duration for tPPOS is 1012. The SN65LVDS302 receiver can tolerate a maximum timing uncertainty defined by tRSKM. The interconnect budget is calculated by:
t int erconnect = t RSKM - t PPOS
(1)
Example: fPCLK(max) = 23 MHz (VGA display resolution, 60 Hz) Transmission mode: 2-ChM; tPPOS(SN65LVDS301) = 330 ps Target bit error rate: 10-12 tRSKM(SN65LVDS302) = 1/(2*15*fPCLK) - 480 ps = 969 ps The interconnect budget for cable skew & ISI needs to be smaller than:
t int erconnect = t RSKM - t PPOS = 639ps
Ideal TPPosn data transition
(2)
D0, D1, D2
Data Period /2
TPPosn(min)
TPPosn(max) RSKM
Ideal receiver strobe position
RSKM
RX internal sampling Clock
Tppos: Transmitter output pulse position (min and max) TPPosx(max) -TPPosx(min) = TJ TXPLL(non-trackable) + tTXskew + tTXDJ
TJ TXPLL(non-trackable): non-trackable TX PLL jitter; this jitter is the integration > f (BWRX); of total jitter above the receiver PLL bandwidth ; TJ TXPLL TJ=RJ[ps-rms]*14 + DJ[ps] t TXskew transmitter output skew (skew between CLK and data) : t TXIDJTransmitter Deterministic JItter of TX output stage (includes TX Intersymbol Interference ISI)
RSPosn (min)
RSKM: Receiver Skew Margin RSKM = SKEW PCB + XTALK PCB + ISIPCB
SKEW XTALK PCB : PCB induced Skew (trace + connector); : PCB induced cross-talk; PCB
RSPosn (max)
RSPosn: Receiver input strobe position (min and max) RSPosn(max) - RSPosn(min) = SkewRX + S&HRX + TJ (RXPLL(non-trackable)
Skew RX: Receiver input skew (skew between CLK and Dx input) S&H RX: Receiver input latch Sample & Hold uncertainty TJ (RXPLL(non-trackable) : Intrinsic RX PLL jitter above RX PLL bandwidth; PLL f(BW RX ); TJ=RJ[ps-rms]*14 + DJ[ps] TJ >
ISI PCB Inter-symbol interference of PCB; is : dependent on interconnect frequency loss; may be zero for short interconnects.
Figure 43. Jitter Budget
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F/S-PIN SETTING AND CONNECTING THE SN65LVDS302 TO AN LCD DRIVER
NOTE:
Receiver PLL tracking: To maximize the design margin for the interconnect, good RX PLL tracking of the TX PLL is important. FlatLink3G requires the RX PLL to have a bandwidth higher the the bandwidth of the TX PLL. The SN65LVDS302 PLL design is optimized to track the SN65LVDS0301 PLL particularly well, thus providing a very large receiver skew margin. A FlatLink3G-compliant link must provide at least 225 ppm of receiver skew margin for the interconnect. It is important to understand the tradeoff between power consumption, EMI, and maximum speed when selecting the F/S signal. It is beneficial to choose the slowest rise time possible to minimize EMI and power consumption. Unfortunately a slower rise time also reduces the timing margin left for the LCD driver. Hence it is necessary to calculate the timing margin to select the correct F/S pin setting. The output rise time depends on the output driver strength and the output load. An LCD driver typical capacitive load is assumed with ~10pF. The higher the capacitive load, the slower will be the rise time. Rise time of the SN65LVDS302 is measured as the time duration it takes the output voltage to rise from 20% of VDD and 80% of VDD and fall time is defined as the time for the output voltage to transition from 80% of VDD down to 20%. Within one mode of operation and one F/S pin setting, the rise time of the output stage is fixed and does not adjust to the pixel frequency. Due to the short bit time at very fast pixel clock speeds and the real capacitive load of the display driver, the output amplitude might not reach VDD and GND saturation fully. To ensure sufficient signal swing and verify the design margin, it becomes necessary to determine that the output amplitude under any circumstance reaches the display driver's input stage logic threshold (usually 30% and 70% of VDD). Figure 44 shows a worst-case rise time simulation assuming a LCD driver load of 16pF at VGA display resolution. PCLK is the fastest switching output. With F/S set to GND (Figure 44-a), the PCLK output voltage amplitude is significantly reduced. The voltage amplitude of the output data RGB[7:0], VS, HS, and DE shows less amplitude attenuation because these outputs carry random data pattern and toggle equal or less than half of the PCLK frequency. It is necessary to determine the timing margin between the LVDS302 output and LCD driver input.
Application: VGA (2-channel mode); F/S set to VDD; Display driver load ~16pF
2.0V 1.8V 1.6V 1.4V 1.2V
VOD VOD
RX rise/fall time
Application: VGA (2-channel mode); F/S set to GND; Display driver load ~16pF
2.0V 1.8V 1.6V 1.4V 1.2V
RX rise/fall time
1.0V 0.8V 0.6V 0.4V 0.2V 0.0V 100ns
(
1.0V 0.8V 0.6V 0.4V 0.2V 0.0V 100ns
The data signal has a slower maximum switching frequency and therefore will drive a larger amplitude than the clock signal
150ns
200ns
250ns
300ns
350ns
400ns
450ns
500ns
550ns
600ns
150ns
200ns
250ns
300ns
350ns
400ns
450ns
500ns
550ns
600ns
clk 22MHz, F/S=1, CL=16 pF
data 22Mbps, F/S=1, CL=16 pF
clk 22MHz, F/S=0, CL=16 pF
data 22Mbps, F/S=0, CL=16 pF
(a)
(b)
Figure 44. Output Amplitude as a Function of Output Toggling Frequency, Capacitive Load and F/S Setting
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HOW TO DETERMINE THE LCD DRIVER TIMING MARGIN
To determine the timing margin, it is necessary to specify the frequency of operation, identify the set-up and hold time of the LCD driver, and specify the output load of the SN65LVDS302 as a combination of the LCD driver input parasitics plus any capacitance caused by the connecting pcb trace. Furthermore, the setting of pin F/S and the SN65LVDS302 output skew impact the margin. The total remaining design margin calculates as following: t rise(max) C LOAD 1 t DM + * t DUTP(max_error) * * t OSK 2 PCLK 10 pF where: tDM- Design Margin fPCLK- Pixel clock frequency tDUTP(max_error)- maximum duty cycle error trise(max)- maximum rise or fall time; see tR/F under switching characteristics CL- parasitic capacitance (sum of LCD driver input parasitics + connecting PCB trace) tskew- clock to data output skew SN65LVDS302
(3)
Example:
At a pixel clock frequeny of 5.5MHz (QVGA), and an assumed LCD driver load of 15 pF, the remaining timing margin is:
t (max) * 50 t DUTP(max_error) + DUTP 100% t DM + 1 * 9ns * 5.5MHz t PCLK + 5% 100% 15pF * 500ps + 57.3ns 1 + 9.1ns 5.5MHz
2
16ns (F S+GND) 10pF
As long as the set-up and hold time of the LCD driver are each less than 57 ns, the timing budget is met sufficiently.
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